View HB54A2569F1_4640999.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

DATA SHEET
256MB, 512MB Registered DDR SDRAM DIMM
HB54A2569F1 (32M words x 72 bits, 1 Bank) HB54A5129F2 (64M words x 72 bits, 2 Banks)
Description
The HB54A2569F1, HB54A5129F2 are Double Data Rate (DDR) SDRAM Module, mounted 256M bits DDR SDRAM (HM5425801BTT) sealed in TSOP package, 1 piece of PLL clock driver, 2 pieces of register driver and 1 piece of serial EEPROM (2k bits EEPROM) for Presence Detect (PD). The HB54A2569F1 is organized as 32M x 72 x 1 bank mounted 9 pieces of 256M bits DDR SDRAM. The HB54A5129F2 is organized as 32M x 72 x 2 banks mounted 18 pieces of 256M bits DDR SDRAM. Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer is realized by the 2 bits prefetch-pipelined architecture. Data strobe (DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. An outline of the products is 184-pin socket type package (dual lead out). Therefore, it makes high density mounting possible without surface mount technology. It provides common data inputs and outputs. Decoupling capacitors are mounted beside each TSOP on the module board.
Features
* 184-pin socket type package (dual lead out) Outline: 133.35mm (Length) x 43.18mm (Height) x 4.00mm (Thickness) Lead pitch: 1.27mm * 2.5V power supply (VCC/VCCQ) * SSTL-2 interface for all inputs and outputs * Clock frequency: 143MHz/133MHz/125MHz (max.) * Data inputs, outputs and DM are synchronized with DQS * 4 banks can operate simultaneously and independently (Component) * Burst read/write operation * Programmable burst length: 2, 4, 8 Burst read stop capability * Programmable burst sequence Sequential Interleave * Start addressing capability Even and Odd * Programmable /CAS latency (CL): 3, 3.5 * 8192 refresh cycles: 7.8s (8192/64ms) * 2 variations of refresh Auto refresh Self refresh
EO
Document No. E0091H40 (Ver. 4.0) Date Published September 2002 (K) Japan URL: http://www.elpida.com
L
This product became EOL in May, 2004.
Elpida Memory, Inc. 2001-2002 Hitachi, Ltd. 2001 Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
Pr
od
t uc
HB54A2569F1, HB54A5129F2
Ordering Information
Part number HB54A2569F1-A75B*1 HB54A2569F1-B75B*2 HB54A2569F1-10B*3 HB54A5129F2-A75B*1 HB54A5129F2-B75B*2 HB54A5129F2-10B*3 Clock frequency MHz (max.) 133 133 100 133 133 100 /CAS latency 3.0 3.5 3.0 3.0 3.5 3.0 Package Contact pad
184-pin dual lead out socket Gold type
Notes: 1. 143MHz operation at /CAS latency = 3.5. 2. 100MHz operation at /CAS latency = 3.0. 3. 125MHz operation at /CAS latency = 3.5.
Pin Configurations
EO
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Pin name VREF DQ0 VSS DQ1 DQS0 DQ2 VCC DQ3 NC /RESET VSS DQ8 DQ9 DQS1 VCCQ NC NC VSS DQ10 DQ11 CKE0 VCCQ DQ16 DQ17 DQS2 VSS
Data Sheet E0091H40 (Ver. 4.0)
Front side 1 pin 52 pin 53 pin 92 pin
93 pin Back side
144 pin 145 pin 184 pin
Pin No. 47
Pin name DQS8 A0 CB2 VSS CB3
Pin No. 93 94 95 96 97
Pin name VSS DQ4 DQ5 VCCQ DM0/DQS9 DQ6 DQ7 VSS NC NC NC
Pin No. 139 140 141 142 143 144 145 146 147 148 149
Pin name VSS DM8/DQS17 A10 CB6 VCCQ CB7 VSS DQ36 DQ37 VCC DM4/DQS13 DQ38 DQ39 VSS DQ44 /RAS DQ45 VCCQ /S0
L
48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
Pr
BA1 98 DQ32 99 VCCQ DQ33 100 101 DQS4 102 DQ34 VSS BA0 DQ35 DQ40 VCCQ /WE DQ41 /CAS VSS DQS5 DQ42 DQ43 VCC NC DQ48 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118
od
VCCQ 150 DQ12 151 DQ13 152 DM1/DQS10 VCC 153 154 DQ14 155 DQ15 156 CKE1 (NC)*1 VCCQ NC 157 158 159 DQ20 A12 VSS 160 161 162 DQ21 A11 163 164
t uc
/S1 (NC)* 1 DM5/DQS14 VSS DQ46 DQ47 NC VCCQ
2
HB54A2569F1, HB54A5129F2
Pin No. 27 28 29 30 31 32 33 34 35 36 37 38 39 Pin name A9 DQ18 A7 VCCQ DQ19 A5 DQ24 VSS DQ25 DQS3 A4 Pin No. 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 Pin name DQ49 VSS NC NC VCCQ DQS6 DQ50 DQ51 VSS VCCID DQ56 DQ57 VCC DQS7 DQ58 DQ59 VSS NC SDA SCL Pin No. 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 Pin name DM2/DQS11 VCC DQ22 A8 DQ23 VSS A6 DQ28 DQ29 VCCQ DM3/DQS12 A3 DQ30 VSS DQ31 CB4 CB5 VCCQ CK0 /CK0 Pin No. 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 Pin name DQ52 DQ53 NC VCC DM6/DQS15 DQ54 DQ55 VCCQ NC DQ60 DQ61 VSS DM7/DQS16 DQ62 DQ63 VCCQ SA0 SA1 SA2 VCCSPD
EO
VCC DQ26 40 41 42 43 44 45 46 DQ27 A2 VSS A1 CB0 CB1 VCC
Data Sheet E0091H40 (Ver. 4.0)
Note: 1. The HB54A2569F1 assign "NC".
L
92
Pr od t uc
3
HB54A2569F1, HB54A5129F2
Pin Description
Pin name A0 to A12 BA0, BA1 DQ0 to DQ63 CB0 to CB7 /RAS /CAS /WE /S0, /S1 Function Address input Row address Column address Data input/output Check bit (Data input/output) Row address strobe command Column address strobe command Write enable Chip select Clock enable Clock input Differential clock input Input and output data strobe Input mask Clock input for serial PD Data input/output for serial PD Serial address input Power for internal circuit Power for DQ circuit Power for serial EEPROM Input reference voltage A0 to A12 A0 to A9
Bank select address
EO
CKE0, CKE1 CK0 /CK0 DQS0 to DQS8 SCL SDA SA0 to SA2 VCC VCCQ VCCSPD VREF VSS VCCID /RESET NC
DM0 to DM8/DQS9 to DQS17
Data Sheet E0091H40 (Ver. 4.0)
L
Pr
Ground VCC identification flag No connection
Reset pin (forces register inputs low)
od t uc
4
HB54A2569F1, HB54A5129F2
Serial PD Matrix*
Byte No. 0 1 2 3 4 5
1
Function described Number of bytes utilized by module manufacturer Total number of bytes in serial PD device Memory type Number of row address Number of column address Number of DIMM banks HB54A2569F1 HB54A5129F2 Module data width Module data width continuation
Bit7 1 0 0 0 0 0 0 0 0
Bit6 0 0 0 0 0 0 0 1 0 0 1 1 0 1 0 0 0 0 0
Bit5 Bit4 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0
Bit3 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 1 1
Bit2 0 0 1 1 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 1 1 1
Bit1 Bit0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 1 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0
Hex value 80H 08H 07H 0DH 0AH 01H 02H 48H 00H 04H 70H 75H 80H 75H 80H 02H 82H 08H 08H 01H 0EH 04H 0CH 01H 02H 26H
Comments 128 256 bytes SDRAM DDR 13 10 1 2 72 bits 0 (+) SSTL 2.5V CL = 2.5*5
6 7 8 9
EO
-B75B -10B 10 -10B 11 12 13 14 15 16 17 18 19 20 21 22 23 -B75B/10B 24 -10B 25 26
Voltage interface level of this assembly 0 0 0 1 0 1 0 1 0 0
DDR SDRAM cycle time, CL = X -A75B
SDRAM access from clock (tAC) -A75B, -B75B
0.75ns*5 0.8ns*5 ECC 7.8 s Self refresh x8 x8 1 CLK 2, 4, 8 4 2, 2.5 0 1 Registered 0.2V CL = 2*5
DIMM configuration type Refresh rate/type
Primary SDRAM width Error checking SDRAM width SDRAM device attributes: Minimum clock delay back-to-back column access SDRAM device attributes: Burst length supported SDRAM device attributes: Number of banks on SDRAM device SDRAM device attributes: /CAS latency SDRAM device attributes: /CS latency SDRAM device attributes: /WE latency SDRAM module attributes SDRAM device attributes: General Minimum clock cycle time at CLX - 0.5 -A75B
Maximum data access time (tAC) from clock at CLX - 0.5 0 -A75B, -B75B 1 Minimum clock cycle time at 0 CLX - 1 Maximum data access time (tAC) from 0 clock at CLX - 1
Data Sheet E0091H40 (Ver. 4.0)
L
Pr
0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 1 1 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0
od
0 0 0 1 1 0 1 1 0 0 0 0 1 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0
C0H 75H
t uc
A0H 75H 0.75ns*5 0.8ns*5 80H 00H 00H
5
HB54A2569F1, HB54A5129F2
Byte No. 27 28 29 30 Function described Minimum row precharge time (tRP) Minimum row active to row active delay (tRRD) Minimum /RAS to /CAS delay (tRCD) Minimum active to precharge time (tRAS) -A75B, -B75B -10B 31 32 Module bank density Address and command setup time before clock (tIS) -A75B, -B75B -10B Bit7 0 0 0 0 0 0 1 1 Bit6 1 0 1 0 0 1 0 0 0 0 1 1 1 1 0 1 1 Bit5 Bit4 0 1 0 1 1 0 0 1 0 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 1 1 1 1 0 1 0 0 0 0 Bit3 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit2 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 Bit1 Bit0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 Hex value 50H 3CH 50H 2DH 32H 40H 90H B0H 90H B0H 50H 60H 50H 60H 00H 41H 46H 4BH 50H 30H 32H 3CH Comments 20ns 15ns 20ns 45ns 50ns 256MB 0.9ns*5 1.1ns*5 0.9ns*5 1.1ns*5 0.5ns*5 0.6ns*5 0.5ns*5 0.6ns*5 Future use 65ns*5 70ns*5 75ns*5 80ns*5 12ns*5 500ps*5 600ps*5 750ps*5 1000ps*5 Future use Initial 202
EO
33 -10B 34 -10B 35 -10B 36 to 40 41 -10B 42 -10B 43 44 -10B 45 -10B 46 to 61 62 63 SPD revision 64 65 to 71 72
Address and command hold time after 1 clock (tIH) -A75B, -B75B 1 0 0 0 0 0 0 0 Data input setup time before clock (tDS) -A75B, -B75B Data input hold time after clock (tDH) -A75B, -B75B
Superset information
Active command period (tRC) -A75B, -B75B
Auto refresh to active/Auto refresh command cycle (tRFC) -A75B, -B75B
SDRAM tCK cycle max. (tCK max.) Dout to DQS skew -A75B, -B75B Data hold skew (tQHS) -A75B, -B75B Superset information Checksum for bytes 0 to 62 HB54A2569F1-A75B HB54A2569F1-B75B HB54A2569F1-10B HB54A5129F2-A75B HB54A5129F2-B75B HB54A5129F2-10B Manufacturer's JEDEC ID code Manufacturer's JEDEC ID code Manufacturing location
Data Sheet E0091H40 (Ver. 4.0)
L
Pr
0 1 0 0 1 0 1 0 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 0 0 1 1 1 1 1 1 0 0 x 0 1 0 0 0 1 1 0 1 1 1 0 0 x 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 x 1 1 1 0 1 0 0 0 x 1 1 1 1 0 0 0 x
od
1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 x 1 0 1 1 1 1 1 1 0 0 1 1 0 0 x x
75H A0H 00H
00H
CAH FAH
t uc
250 BFH 191 CBH FBH 203 251 192 C0H 07H HITACHI 00H xx *2 (ASCII-8bit code)
6
HB54A2569F1, HB54A5129F2
Byte No. 73 74 75 76 77 78 Function described Module part number Module part number Module part number Module part number Module part number Module part number HB54A2569F1 HB54A5129F2 79 Module part number HB54A2569F1 HB54A5129F2 80 Module part number HB54A2459F1 HB54A5129F2 Bit7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit6 1 1 0 0 1 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 Bit5 Bit4 0 0 1 1 0 1 1 1 1 1 1 1 0 1 1 1 0 0 1 1 1 0 0 1 1 0 1 1 1 1 1 1 1 0 1 1 0 0 0 1 1 1 Bit3 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 Bit2 0 0 1 1 0 0 1 1 0 1 0 0 1 0 0 1 0 0 0 1 0 1 0 0 0 Bit1 Bit0 0 1 0 0 0 1 0 0 0 1 1 0 1 0 1 0 0 1 0 1 0 0 1 1 0 0 0 1 0 1 0 1 1 1 0 0 1 0 1 0 1 1 0 1 1 0 1 0 0 0 Hex value 48H 42H 35H 34H 41H 32H 35H 35H 31H 36H 32H 39H 46H 31H 32H 2DH 41H 42H 31H 37H 30H 35H 42H 42H 20H Comments H B 5 4 A 2 5 5 1 6 2 9 F 1 2 -- A B 1 7 0 5 B B (Space) (Space) Initial (Space) Year code (BCD) Week code (BCD)
EO
81 82 83 HB54A5129F2 84 85 -B75B -10B 86 -10B 87 -10B 88 -10B 89 to 90 91 92 93 94 95 to 98 99 to 127 Revision code Revision code
Module part number Module part number Module part number HB54A2569F1 Module part number
Module part number -A75B
Module part number -A75B, -B75B Module part number -A75B, -B75B Module part number -A75BB, -B75B Module part number
Manufacturing date Manufacturing date Module serial number Manufacturer specific data
Notes: 1. All serial PD data are not protected. 0: Serial data, "driven Low", 1: Serial data, "driven High" These SPD are based on JEDEC Committee Ballot JC-42.5-99-129. 2. Byte72 is manufacturing location code. (ex: In case of Japan, byte72 is 4AH. 4AH shows "J" on ASCII code.) 3. Bytes 95 through 98 are assembly serial number. 4. All bits of 99 through 127 are not defined ("1" or "0"). 5. These specifications are defined based on component specification, not module.
Data Sheet E0091H40 (Ver. 4.0)
L
Pr
0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 x x *3 *4 0 0 0 x x 1 0 0 1 1 1 0 0 0 x x x x x x
od
0 0 0 0 0 0 0 0 0 x x x x x x
20H 30H 20H xx xx
t uc
7
HB54A2569F1, HB54A5129F2
Block Diagram (HB54A2569F1)
RS0 RS DQS0 8 DQ0 to DQ7 RS DQS1 8 DQ8 to DQ15 RS DQS2 8 DQ16 to DQ23 RS DQS3 8 DQ24 to DQ31 RS DQS4 8 DQ32 to DQ39 RS DQS5 8 DQ40 to DQ47 RS DQS6 8 RS RS DQS7 8 RS RS DQS8 DQS DQ /CS DM RS DM8/DQS17 DQS DQ /CS DM DQS DQ /CS DM RS DM7/DQS16 DQ48 to DQ55 RS DQS DQ /CS DM RS DM6/DQS15 RS DQS DQ /CS DM RS DM5/DQS14 RS DQS DQ /CS DM RS DM4/DQS13 RS DQS DQ /CS DM RS DM3/DQS12 RS DQS DQ /CS DM RS DM2/DQS11 RS DQS DQ /CS DM RS DM1/DQS10 RS DM0/DQS9
D0
D1
D2
EO
/S0 BA0 to BA1 A0 to A12 /RAS /CAS CKE0 /WE
RS RS RS RS RS RS RS
D3
D4
D5
Data Sheet E0091H40 (Ver. 4.0)
L
R E G I S T E R PCK /PCK
D6
DQ56 to DQ63
D7
Pr
8 RS CB0 to CB7
D8
/RS0 -> /CS: SDRAMs D0 to D8
RBA0 to RBA1 -> BA0 to BA1: SDRAMs D0 to D8 RA0 to RA12 -> A0 to A12: SDRAMs D0 to D8 /RRAS -> /RAS: SDRAMs D0 to D8 /RCAS -> /CAS: SDRAMs D0 to D8
* D0 to D8: HM5425801 U0: 2k-bits EEPROM RS: 22 PLL: CDCV857 Register: SSTV16857 Serial PD
RCKE0A -> CKE: SDRAMs D0 to D8 /RWE -> /WE: SDRAMs D0 to D8 /RESET
od
SCL SCL SDA
SDA
U0
A1
VCCQ VCC VREF VSS VCCID open
D0 to D8 D0 to D8 D0 to D8 D0 to D8
A0
A2
CK0, /CK0 PLL* Note: Wire per Clock loading table/Wiring diagrams.
SA0 SA1 SA2 Notes: 1. The SDA pull-up resistor is required due to the open-drain/open-collector output. 2. The SCL pull-up resistor is recommended because of the normal SCL line inacitve "high" state.
t uc
8
HB54A2569F1, HB54A5129F2
Block Diagram (HB54A5129F2)
/RS1 /RS0 RS DQS0 8 DQ0 to DQ7 RS DQS1 8 DQ8 to DQ15 RS DQS2 8 DQ16 to DQ23 RS 8 RS RS 8 RS RS 8 RS RS RS RS RS RS RS DQS DQ /CS DM DQS DQ /CS DM RS DM6/DQS15 /CS DM DQS DQ /CS DM RS DM7/DQS16 /CS DM DQS DQ /CS DM RS DM8/DQS17 DQS DQ /CS DM DQS DQ /CS DM RS DM5/DQS14 DQS DQ /CS DM DQS DQ /CS DM RS DM4/DQS13 RS DQS DQ /CS DM DQS DQ /CS DM RS DM3/DQS12 RS DQS DQ /CS DM DQS DQ /CS DM RS DM2/DQS11 RS DQS DQ /CS DM DQS DQ /CS DM RS DM1/DQS10 RS DM0/DQS9
D0
D9
D1
D10
D2
D11
EO
A0 to A12 BA0 to BA1 /RAS /CAS /WE /S0 CKE0 /S1 CKE1 PCK /PCK
DQS3
DQ24 to DQ31 DQS4
D3
D12
DQ32 to DQ39 DQS5
D4
D13
DQ40 to DQ47 DQS6
D5
D14
Data Sheet E0091H40 (Ver. 4.0)
L
8 DQ48 to DQ55 DQS7 8 DQ56 to DQ63 DQS8 8 CB0 to CB7
RS RS RS RS RS RS RS RS RS
DQS DQ
D6
D15
DQS DQ
D7
D16
Pr
DQS DQ /CS DM DQS DQ /CS DM
D8
D17
R E G I S T E R
RA0 to RA12 -> A0 to A12: SDRAMs D0 to D17
RBA0 to RBA1 -> BA0 to BA1: SDRAMs D0 to D17 /RRAS -> /RAS: SDRAMs D0 to D17 /RCAS -> /CAS: SDRAMs D0 to D17 /RWE -> /WE: SDRAMs D0 to D17 /RS0 -> /CS: SDRAMs D0 to D8
* D0 to D17: HM5425801 U0: 2k bits EEPROM RS: 22 PLL: CDCV857 Register: SSTV16857 /RS0 and /RS1 alternate between the back and front side of the DIMM. Serial PD
RCKE0 -> CKE: SDRAMs D0 to D8 /RS1 -> /CS: SDRAMs D9 to D17
RCKE1 -> CKE: SDRAMs D9 to D17 /RESET
od
SCL SCL SDA
SDA
U0
A1
A0
A2
VCCQ VCC VREF VSS VCCID
open
D0 to D17 D0 to D17 D0 to D17 D0 to D17
SA0 SA1 SA2 Notes: 1. The SDA pull-up resistor is required due to the open-drain/open-collector output. 2. The SCL pull-up resistor is recommended because of the normal SCL line inacitve "high" state.
t uc
CK0, /CK0 PLL* Note: Wire per Clock loading table/Wiring diagrams.
9
HB54A2569F1, HB54A5129F2
Differential Clock Net Wiring (CK0, /CK0)
0ns (nominal) SDRAM stack 120
PLL OUT1
CK0
120 IN
SDRAM stack 240 Register1
EO
/CK0
120
OUT'N'
(Typically two registers per DIMM)
C Feedback 240 Register2
Notes: 1. The clock delay from the input of the PLL clock to the input of any SDRAM or register willl be set to 0 ns (nominal). 2. Input, output and feedback clock lines are terminated from line to line as shown, and not from line to ground. 3. Only one PLL output is shown per output type. Any additional PLL outputs will be wired in a similar manner. 4. Termination resistors for feedback path clocks are located after the pins of the PLL.
Data Sheet E0091H40 (Ver. 4.0)
L
Pr
10
od t uc
HB54A2569F1, HB54A5129F2
Pin Functions (1)
CK (CLK), /CK (/CLK) (input pin): The CK and the /CK are the master clock inputs. All inputs except DMs, DQSs and DQs are referred to the cross point of the CK rising edge and the VREF level. When a read operation, DQSs and DQs are referred to the cross point of the CK and the /CK. When a write operation, DMs and DQs are referred to the cross point of the DQS and the VREF level. DQSs for write operation are referred to the cross point of the CK and the /CK. /S (/CS) (input pin): When /S is Low, commands and data can be input. When /S is High, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held. /RAS, /CAS, and /WE (input pins): These pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels. See "Command operation".
EO
Pin Functions (2)
A0 to A12 (input pins): Row address (AX0 to AX12) is determined by the A0 to the A12 level at the cross point of the CK rising edge and the VREF level in a bank active command cycle. Column address (AY0 to AY9) is loaded via the A0 to the A9, the A11 at the cross point of the CK rising edge and the VREF level in a read or a write command cycle. This column address becomes the starting address of a burst operation. A10 (AP) (input pin): A10 defines the precharge mode when a precharge command, a read command or a write command is issued. If A10 = High when a precharge command is issued, all banks are precharged. If A10 = Low when a precharge command is issued, only the bank that is selected by BA1, BA0 is precharged. If A10 = High when read or write command, auto-precharge function is enabled. While A10 = Low, auto-precharge function is disabled. BA0, BA1 (input pin): BA0/BA1 are bank select signals. The memory array is divided into bank 0, bank 1, bank 2 and bank 3. If BA1 = Low and BA0 = Low, bank 0 is selected. If BA1 = High and BA0 = Low, bank 1 is selected. If BA1 = Low and BA0 = High, bank 2 is selected. If BA1 = High and BA0 = High, bank 3 is selected. CKE (input pin): CKE controls power down and self-refresh. The power down and the self-refresh commands are entered when the CKE is driven Low and exited when it resumes to High. The CKE level must be kept for 1 CK cycle (= LCKEPW) at least, that is, if CKE changes at the cross point of the CK rising edge and the VREF level with proper setup time tIS, at the next CK rising edge CKE level must be kept with proper hold time tIH.
DM (input pins): DM is the reference signals of the data input mask function. DMs are sampled at the cross point of DQS and VREF. DQ, CB (input and output pins): Data are input to and output from these pins.
DQS (input and output pin): DQS provide the read data strobes (as output) and the write data strobes (as input). VCC and VCCQ (power supply pins): 2.5V is applied. (VCC is for the internal circuit and VCCQ is for the output buffer.) VCCSPD (power supply pin): 2.5V is applied (For serial EEPROM). VSS (power supply pin): Ground is connected.
/RESET (input pin): LVCMOS reset input. When /RESET is low, all registers are reset and all outputs are low.
Data Sheet E0091H40 (Ver. 4.0)
L
Pr
11
od
t uc
HB54A2569F1, HB54A5129F2
Detailed Operation Part, AC Characteristics and Timing Waveforms
Refer to the HM5425161B/HM5425801B/HM5425401B Series datasheet (E0086H). DIMM /CAS latency = Device CL + 1 for registered type.
Electrical Specifications
Absolute Maximum Ratings
Parameter Voltage on any pin relative to VSS Supply voltage relative to VSS Short circuit output current Power dissipation Symbol VT VCC, VCCQ IOUT PT Topr Tstg Value -1.0 to +4.6 -1.0 to +4.6 50 9 0 to +55 -50 to +100 Unit V V mA W C C Note 1 1
EO
Operating temperature Storage temperature Parameter Supply voltage Input reference voltage Termination voltage DC Input high voltage DC Input low voltage DC Input signal voltage DC differential input voltage
Notes: 1. Respect to VSS. DC Operating Conditions (TA = 0 to +55C)
Symbol VCC, VCCQ VSS VREF VTT VIH VIL VIN (dc) min. 2.3 0 1.15 VREF - 0.04 VREF + 0.18 -0.3 -0.3 Typ 2.5 0 1.25 VREF -- -- -- -- max. 2.7 0 1.35 VREF + 0.04 VCCQ + 0.3 VREF - 0.18 VCCQ + 0.3 VCCQ + 0.6 Unit V V V V V V V V 1 1 1, 3 1, 4 5 6 Notes 1, 2
L
Pr
VSWING (dc) 0.36
Notes: 1. 2. 3. 4. 5. 6.
All parameters are referred to VSS, when measured. VCCQ must be lower than or equal to VCC. VIH is allowed to exceed VCC up to 4.6V for the period shorter than or equal to 5ns. VIL is allowed to outreach below VSS down to -1.0V for the period shorter than or equal to 5ns. VIN (dc) specifies the allowable dc execution of each differential input. VSWING (dc) specifies the input differential voltage required for switching.
od
12
t uc
Data Sheet E0091H40 (Ver. 4.0)
HB54A2569F1, HB54A5129F2
DC Characteristics 1 (TA = 0 to 55C, VCC, VCCQ = 2.5V 0.2V, VSS = 0V)
HB54A2569F1 Parameter Operating current (ACTV-PRE) Operating current (ACTV-READ-PRE) Idle power down standby current Idle standby current Symbol ICC0 Grade -A75B -B75B -10B -A75B -B75B -10B -A75B -B75B -10B -A75B -B75B -10B -A75B -B75B -10B -A75B -B75B -10B -A75B -B75B -10B -A75B -B75B -10B -A75B -B75B -10B -A75B -B75B -10B max. 1294 1241 1099 1789 1691 1549 556 521 487 754 701 649 619 556 514 844 791 739 2419 2321 2224 2239 2141 2044 2239 2186 1999 421 413 406 HB54A5129F2 max. 1744 1646 1459 2239 2096 1909 718 656 595 1114 1016 919 844 746 649 1294 1196 1099 2869 2726 2584 2689 2546 2404 2689 2591 2359 448 440 433 Unit mA Test condition CKE VIH, tRC = min. Notes 1, 2, 5
ICC1
mA
CKE VIH, BL = 2, 1, 2, 5 CL = 3.5, tRC = min. CKE VIL CKE VIH, /CS VIH CKE VIL CKE VIH, /CS VIH tRAS = max. CKE VIH, BL = 2, CL = 3.5 CKE VIH, BL = 2, CL = 3.5 tRFC = min., Input VIL or VIH Input VCC - 0.2V Input 0.2V. 4
ICC2P
mA
ICC2N
mA
4
EO
Active standby current Operating current (Burst read operation) Operating current (Burst write operation) Auto refresh current Self refresh current
Active power down standby ICC3P current ICC3N
mA
3
mA
3
ICC4R
mA
1, 2, 5, 6
L
ICC4W ICC5 ICC6 Symbol ILI ILO VOH VOL
mA
1, 2, 5, 6
mA
Pr
min. -10 -10 VTT + 0.76 -- max. 10 10 -- VTT - 0.76
mA
Notes. 1. 2. 3. 4. 5. 6. 7.
These ICC data are measured under condition that DQ pins are not connected. One bank operation. One bank active. All banks idle. Command/Address transition once per one cycle. Data/Data mask transition twice per one cycle. The ICC data on this table are measured with regard to tCK = min. in general.
DC Characteristics 2 (TA = 0 to 55C, VCC, VCCQ = 2.5V 0.2V, VSS = 0V)
Parameter Input leakage current Output leakage current Output high voltage Output low voltage Unit A
od
A V V
Test condition
Notes
VCC VIN VSS
t uc
VCC VOUT VSS IOH (max.) = -15.2mA IOL (min.) = 15.2mA
Data Sheet E0091H40 (Ver. 4.0)
13
HB54A2569F1, HB54A5129F2
Pin Capacitance (TA = 25C, VCC, VCCQ = 2.5V 0.2V) [HB54A2569F1]
Parameter Input capacitance Input capacitance Data and DQS input/output capacitance Symbol CI1 CI2 CO Pins Address, /RAS, /CAS, /WE, /S, CKE CK, /CK DQ, DQS, CB, DM max. 10 20 15 Unit pF pF pF Notes 1, 3 1, 3 1, 2, 3
[HB54A5129F2]
Parameter Input capacitance Symbol CI1 CI2 CO Pins Address, /RAS, /CAS, /WE, /S, CKE CK, /CK DQ, DQS, CB, DM max. 10 20 20 Unit pF pF pF Notes 1, 3 1, 3 1, 2, 3
EO
Input capacitance Data and DQS input/output capacitance Parameter (CL = 3.5) (CL = 3.5) (CL = 3.5) (CL = 3.5) Write recovery Power down entry CKE minimum pulse width
Notes: 1. These parameters are measured on conditions: f = 100MHz, VOUT = VCCQ/2, VOUT = 0.2V. 2. Dout circuits are disabled. 3. This parameter is sampled and not 100% tested. Timing Parameter Measured in Clock Cycle for Registered DIMM
Write to pre-charge command delay (same bank) Read to pre-charge command delay (same bank) Write to read command delay (to input all data) Burst stop command to write command delay (CL = 3) Burst stop command to DQ High-Z (CL = 3)
Read command to write command delay (to output all data) (CL = 3) Pre-charge command to High-Z (CL = 3) Write command to data in latency
Register set command to active or register set command Self refresh exit to non-read command Self refresh exit to read command
Power down exit to command input
Data Sheet E0091H40 (Ver. 4.0)
L
Number of clock cycle Symbol tWPD tRPD tWRD min. 3 + BL/2 BL/2 2 + BL/2 2 3 3 3.5 2 + BL/2 max.
Pr
tBSTW tBSTW tBSTZ tBSTZ tRWD tRWD tHZP tHZP tWCD tWR tMRD tSNR tSRD tPDEN tPDEX tCKEPW
od
3 + BL/2 3 3.5 2 1 2 10 200 1 1 1
t uc
14
HB54A2569F1, HB54A5129F2
Physical Outline
Unit: mm 133.35 0.15 128.95 4.00 max (64.48) (DATUM -A-)
2.30
Component area (Front)
1 B 64.77 49.53 A 92
1.27 0.10
2 - 2.50 0.10
93
10.00
184
4.00 min
4.00 0.10
2.50 0.20
0.20 0.15
3.80
EO
R 2.00
Component area (Back)
3.00 min
Detail A
Detail B 1.27 typ 6.62 2.175 R 0.90 (DATUM -A-)
6.35
1.00 0.05
1.80 0.10
Note: Tolerance on all dimensions 0.13 unless otherwise specified.
ECA-TS2-0059-01
Data Sheet E0091H40 (Ver. 4.0)
15
43.18 0.15
17.80
L
Pr
od
t uc
HB54A2569F1, HB54A5129F2
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory ICs, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these components to prevent damaging them. In particular, do not push module cover or drop the modules in order to protect from mechanical defects, which would be electrical defects. When re-packing memory modules, be sure the modules are not touching each other. Modules in contact with other modules may cause excessive mechanical stress, which may damage the modules.
MDE0202
NOTES FOR CMOS DEVICES
EO
1 2 3
PRECAUTION AGAINST ESD FOR MOS DEVICES
Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it.
HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications.
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function.
Data Sheet E0091H40 (Ver. 4.0)
L
Pr
16
od
t uc
CME0107
HB54A2569F1, HB54A5129F2
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [Product applications] Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. [Usage environment] This product is not designed to be resistant to electromagnetic waves or radiation. This product must be used in a non-condensing environment. If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations.
EO
Data Sheet E0091H40 (Ver. 4.0)
L
Pr
17
M01E0107
od t uc

▲Up To Search▲

Price & Availability of HB54A2569F1

	To Download HB54A2569F1 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .